The present invention relates to semiconductor devices, and can be suitably used for the semiconductor devices incorporating an SRAM (Static Random Access Memory), for example.
As miniaturization of semiconductor devices proceeds, it is becoming more difficult to meet the criteria of a drop of a power supply voltage, power EM (ElectroMigration), and the like. As the countermeasure therefor, adding power supply terminals and/or adding power supply vias are known, but in either case, the interconnectivity might be degraded.
In connection with the above description, Patent Document 1 (Japanese Patent Laid-Open No. 2001-36049) discloses a description of a semiconductor memory device. This semiconductor memory device includes a plurality of MIS transistors, a main bit line, a sub bit line, a first switching element, a first source line, a second source line, and a word line. Here, the MIS transistors each have a floating gate, a control gate, a source, and a drain. The sub bit line is provided for each set formed for every multiple MIS transistors of a plurality of MIS transistors. The first switching element selectively couples the sub bit line to the main bit line. The first source line is coupled in common to the sources of the multiple MIS transistors in a plurality of sets. The second source line is coupled in common to the sources of the multiple MIS transistors in each of the sets, to which the first source line is not coupled. The word line couples one control gate of multiple MIS transistors in one set to one control gate of multiple MIS transistors in other set. The word line coupled to the control gate of the MIS transistors each having the source, to which the first source line is coupled, includes a first wiring and a second wiring. Here, the first wiring includes a first nonmetallic electric conductor. The second wiring includes metal, and is disposed in a layer different from that of the first wiring and is coupled to the first wiring. The word line coupled to the control gate of multiple MIS transistors each having the source, to which the second source line is coupled, includes a first layer wiring. The first source line and the sub bit line include a second nonmetallic electric conductor. The second source line includes metal.
Moreover, Patent Document 2 (Japanese Patent Laid-Open No. 2008-227130) discloses a description of a semiconductor integrated circuit. A plurality of standard cells is arranged in this semiconductor integrated circuit. This semiconductor integrated circuit includes a first cell power supply wiring, a second cell power supply wiring, a first upper-layer power supply wiring, and a second upper-layer power supply wiring. Here, the first cell power supply wiring extends in one direction, and supplies current to the standard cells. The second cell power supply wiring is wired in parallel to the first cell power supply wiring, and supplies current to the standard cells. The first upper-layer power supply wiring is wired perpendicularly to the first and second cell power supply wirings, in an upper layer of the first and second cell power supply wirings, and is coupled to the first cell power supply wiring through a via. The second upper-layer power supply wiring is wired perpendicularly to the first and second cell power supply wirings, in an upper layer of the first and second cell power supply wirings, and is coupled to the second cell power supply wiring through a via. In a region overlapping with the first upper-layer power supply wiring and including a portion, in which a via coupling the first cell power supply wiring and the first upper-layer power supply wiring is disposed, the first cell power supply wiring includes a first wide portion with a width wider than the width of a region not overlapping with the first and second upper-layer power supply wirings.
Furthermore, Patent Document 3 (Japanese Patent Laid-Open No. 2009-49034) discloses a description of a semiconductor device. This semiconductor device includes an interlayer insulating film, a lower wiring layer, an upper wiring layer, and a via hole. Here, the lower wiring layer is disposed on the lower side of the interlayer insulating film. The upper wiring layer is disposed on the upper side of the interlayer insulating film. The via hole extends through the interlayer insulating film, and electrically couples a wiring belonging to the lower wiring layer and a wiring belonging to the upper wiring layer. This semiconductor device has the following features. That is, a plurality of wiring lines and a contact region are provided. Here, the wiring lines extend along a predetermined direction in the lower wiring layer. The contact region is formed by partially coupling at least two wiring lines, and contacts with a via hole. Moreover, in the wiring lines, a void is present in a first interlayer insulating film located between wiring lines adjacent to each other. In a second interlayer insulating film located between a contact portion of the via hole in the contact region and a wiring line adjacent to the contact region, a void is not present.
Moreover, Patent Document 4 (Japanese Patent Laid-Open No. 2011-14637) discloses a description of a semiconductor device. This semiconductor device includes first and second wirings, third and fourth wirings, a fifth wiring, a first contact conductor, and a second contact conductor. Here, the first and second wirings are provided in a first wiring layer and extend in parallel in a first direction. The third and fourth wirings are provided in a second wiring layer and extend in parallel in a second direction intersecting the first direction. The fifth wiring is provided in a third wiring layer located between the first wiring layer and the second wiring layer. The first contact conductor couples the first wiring and the third wiring. The second contact conductor couples the second wiring and the fourth wiring. Moreover, the first and second contact conductors are arranged in the first direction.